library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity judge is
port(
		clk: in std_ulogic;
		inflag: in std_ulogic;
		frame: in integer range 0 to 4096; --rate adaptation
		addr1: in std_ulogic_vector(15 downto 0); 
		addr2: in std_ulogic_vector(15 downto 0); 
		addr3: in std_ulogic_vector(15 downto 0); 
		addr4: in std_ulogic_vector(15 downto 0); 
		addr5: in std_ulogic_vector(15 downto 0); 
		addr6: in std_ulogic_vector(15 downto 0); 
		addr7: in std_ulogic_vector(15 downto 0); 
		addr8: in std_ulogic_vector(15 downto 0); 
		b1: in std_ulogic_vector(31 downto 0);
		b2: in std_ulogic_vector(31 downto 0);
		b3: in std_ulogic_vector(31 downto 0);
		b4: in std_ulogic_vector(31 downto 0);
		b5: in std_ulogic_vector(31 downto 0);
		b6: in std_ulogic_vector(31 downto 0);
		b7: in std_ulogic_vector(31 downto 0);
		b8: in std_ulogic_vector(31 downto 0); 
		b_len: in integer range 50 to 512;
		--judge_flag: out std_logic;
		softbits: out std_ulogic_vector(31 downto 0)
		--b: out std_logic
		);
end judge;

architecture bev of judge is

signal t1,t2:signed(18 downto 0);
signal temp1,temp2:std_ulogic_vector(18 downto 0);
signal t11,t22:std_ulogic_vector(3 downto 0);
signal bb1,bb2,bb3,bb4,bb5,bb6,bb7,bb8 : std_ulogic_vector(15 downto 0);
signal bbb1,bbb2,bbb3,bbb4,bbb5,bbb6,bbb7,bbb8 : std_ulogic_vector(15 downto 0);


begin

--*********************the first depth data operation*************
process(clk,inflag,frame,b_len,b1(31 downto 16),b2(31 downto 16),b3(31 downto 16),b4(31 downto 16),b5(31 downto 16),b6(31 downto 16),b7(31 downto 16),b8(31 downto 16),addr1(15 downto 8),addr2(15 downto 8),addr3(15 downto 8),addr4(15 downto 8),addr5(15 downto 8),addr6(15 downto 8),addr7(15 downto 8),addr8(15 downto 8))
variable var : unsigned(12 downto 0);
variable temp:integer range 0 to 4096;
begin
  if inflag='1' then
  if clk'event and clk='1' then
   if frame <= (b_len-1) and frame >= 0 then --[0,49]
		temp:=(frame);
		var := to_unsigned(temp,13);
		if unsigned(addr1(15 downto 8)) < var then
		    bb1 <= b1(31 downto 16);
		else
		    bb1 <= (others=>'0');
		end if;
		bb2 <= (others=>'0');
		bb3 <= (others=>'0');
		bb4 <= (others=>'0');
		bb5 <= (others=>'0');
		bb6 <= (others=>'0');
		bb7 <= (others=>'0');
		bb8 <= (others=>'0');
		
	elsif frame <= (2*b_len-1) and frame > (b_len-1) then --(49,99]
		temp:=(frame-b_len);
	   var := to_unsigned(temp,13);
		bb1 <= b1(31 downto 16);
		if unsigned(addr2(15 downto 8)) < var then
		    bb2 <= b2(31 downto 16);
	   else
	      bb2 <= (others=>'0');
      end if;
		bb3 <= (others=>'0');
		bb4 <= (others=>'0');
		bb5 <= (others=>'0');
		bb6 <= (others=>'0');
		bb7 <= (others=>'0');
		bb8 <= (others=>'0');
		
	elsif frame <= (3*b_len-1) and frame > (2*b_len-1) then --(99,149]
		temp:=(frame-2*b_len);
	   var := to_unsigned(temp,13);
		bb1 <= b1(31 downto 16);
		bb2 <= b2(31 downto 16);
		if unsigned(addr3(15 downto 8)) < var then
		    bb3 <= b3(31 downto 16);
	   else
	       bb3 <= (others=>'0');
	   end if;
		bb4 <= (others=>'0');
		bb5 <= (others=>'0');
		bb6 <= (others=>'0');
		bb7 <= (others=>'0');
		bb8 <= (others=>'0');
		
	elsif frame <= (4*b_len-1) and frame > (3*b_len-1) then --(149,199]
		temp:=(frame-3*b_len);
	   var := to_unsigned(temp,13);
		bb1 <= b1(31 downto 16);
		bb2 <= b2(31 downto 16);
		bb3 <= b3(31 downto 16);
		if unsigned(addr4(15 downto 8)) < var then
		    bb4 <= b4(31 downto 16);
      else
	       bb4 <= (others=>'0');
   	end if;
		bb5 <= (others=>'0');
		bb6 <= (others=>'0');
		bb7 <= (others=>'0');
		bb8 <= (others=>'0');
		
	elsif frame <= (5*b_len-1) and frame > (4*b_len-1) then --(199,249]
		temp:=(frame-4*b_len);
	   var := to_unsigned(temp,13);
		bb1 <= b1(31 downto 16);
		bb2 <= b2(31 downto 16);
		bb3 <= b3(31 downto 16);
		bb4 <= b4(31 downto 16);
		if unsigned(addr5(15 downto 8)) < var then
		    bb5 <= b5(31 downto 16);
	   else
	      bb5 <= (others=>'0');
	   end if;
		bb6 <= (others=>'0');
		bb7 <= (others=>'0');
		bb8 <= (others=>'0');
		
	elsif frame <= (6*b_len-1) and frame > (5*b_len-1) then --(249,299]
		temp:=(frame-5*b_len);
	   var := to_unsigned(temp,13);
		bb1 <= b1(31 downto 16);
		bb2 <= b2(31 downto 16);
		bb3 <= b3(31 downto 16);
		bb4 <= b4(31 downto 16);
		bb5 <= b5(31 downto 16);
		if unsigned(addr6(15 downto 8)) < var then
		    bb6 <= b6(31 downto 16);
	   else
	      bb6 <= (others=>'0');
	   end if;
		bb7 <= (others=>'0');
		bb8 <= (others=>'0');
		
	elsif frame <= (7*b_len-1) and frame > (6*b_len-1) then --(299,349]
		temp:=(frame-6*b_len);
	   var := to_unsigned(temp,13);
		bb1 <= b1(31 downto 16);
		bb2 <= b2(31 downto 16);
		bb3 <= b3(31 downto 16);
		bb4 <= b4(31 downto 16);
		bb5 <= b5(31 downto 16);
		bb6 <= b6(31 downto 16);
		if unsigned(addr7(15 downto 8)) < var then
		    bb7 <= b7(31 downto 16);
	   else
	       bb7 <= (others=>'0');
	   end if;
		bb8 <= (others=>'0');
		
	elsif frame <= (8*b_len-1) and frame > (7*b_len-1) then --(349,399]
		temp:=(frame-7*b_len);
	   var := to_unsigned(temp,13);
		bb1 <= b1(31 downto 16);
		bb2 <= b2(31 downto 16);
		bb3 <= b3(31 downto 16);
		bb4 <= b4(31 downto 16);
		bb5 <= b5(31 downto 16);
		bb6 <= b6(31 downto 16);
		bb7 <= b7(31 downto 16);
		if unsigned(addr8(15 downto 8)) < var then
		    bb8 <= b8(31 downto 16);
	   else
	       bb8 <= (others=>'0');
	   end if;
	  
	else
		bb1 <= b1(31 downto 16);
		bb2 <= b2(31 downto 16);
		bb3 <= b3(31 downto 16);
		bb4 <= b4(31 downto 16);
		bb5 <= b5(31 downto 16);
		bb6 <= b6(31 downto 16);
		bb7 <= b7(31 downto 16);
		bb8 <= b8(31 downto 16);
	end if;
	end if;
end if;
end process;

process(clk,inflag,b1,bb2,bb3,bb4,bb5,bb6,bb7,bb8)
  begin
    if inflag='1' then
    if clk'event and clk='1' then
t1 <= signed(bb1(15)&bb1(15)&bb1(15)&bb1) +
		  signed(bb2(15)&bb2(15)&bb2(15)&bb2) +
		  signed(bb3(15)&bb3(15)&bb3(15)&bb3) +
		  signed(bb4(15)&bb4(15)&bb4(15)&bb4) +
		  signed(bb5(15)&bb5(15)&bb5(15)&bb5) +
		  signed(bb6(15)&bb6(15)&bb6(15)&bb6) +
		  signed(bb7(15)&bb7(15)&bb7(15)&bb7) +
		  signed(bb8(15)&bb8(15)&bb8(15)&bb8);
		  end if;
		  end if;
end process;
		  
temp1 <= std_ulogic_vector(t1);
softbits(31 downto 16) <= temp1(18 downto 3);

--*********************the second depth data operation*************
process(clk,inflag,frame,b_len,b1(15 downto 0),b2(15 downto 0),b3(15 downto 0),b4(15 downto 0),b5(15 downto 0),b6(15 downto 0),b7(15 downto 0),b8(15 downto 0),addr1(7 downto 0),addr2(7 downto 0),addr3(7 downto 0),addr4(7 downto 0),addr5(7 downto 0),addr6(7 downto 0),addr7(7 downto 0),addr8(7 downto 0))
variable var : unsigned(12 downto 0);
variable temp:integer range 0 to 4096;
begin
  if inflag='1' then
  if clk'event and clk='1' then
   if frame <= (b_len-1) and frame >= 0 then --[0,49]
		temp:=(frame);
		var := to_unsigned(temp,13);
		if unsigned(addr1(7 downto 0)) < var then
		    bbb1 <= b1(15 downto 0);
		else
		    bbb1 <= (others=>'0');
		end if;
		bbb2 <= (others=>'0');
		bbb3 <= (others=>'0');
		bbb4 <= (others=>'0');
		bbb5 <= (others=>'0');
		bbb6 <= (others=>'0');
		bbb7 <= (others=>'0');
		bbb8 <= (others=>'0');
		
	elsif frame <= (2*b_len-1) and frame > (b_len-1) then --(49,99]
		temp:=(frame-b_len);
	   var := to_unsigned(temp,13);
		bbb1 <= b1(15 downto 0);
		if unsigned(addr2(7 downto 0)) < var then
		    bbb2 <= b2(15 downto 0);
	   else
	      bbb2 <= (others=>'0');
      end if;
		bbb3 <= (others=>'0');
		bbb4 <= (others=>'0');
		bbb5 <= (others=>'0');
		bbb6 <= (others=>'0');
		bbb7 <= (others=>'0');
		bbb8 <= (others=>'0');
		
	elsif frame <= (3*b_len-1) and frame > (2*b_len-1) then --(99,149]
		temp:=(frame-2*b_len);
	   var := to_unsigned(temp,13);
		bbb1 <= b1(15 downto 0);
		bbb2 <= b2(15 downto 0);
		if unsigned(addr3(7 downto 0)) < var then
		    bbb3 <= b3(15 downto 0);
	   else
	       bbb3 <= (others=>'0');
	   end if;
		bbb4 <= (others=>'0');
		bbb5 <= (others=>'0');
		bbb6 <= (others=>'0');
		bbb7 <= (others=>'0');
		bbb8 <= (others=>'0');
		
	elsif frame <= (4*b_len-1) and frame > (3*b_len-1) then --(149,199]
		temp:=(frame-3*b_len);
	   var := to_unsigned(temp,13);
		bbb1 <= b1(15 downto 0);
		bbb2 <= b2(15 downto 0);
		bbb3 <= b3(15 downto 0);
		if unsigned(addr4(7 downto 0)) < var then
		    bbb4 <= b4(15 downto 0);
      else
	       bbb4 <= (others=>'0');
   	end if;
		bbb5 <= (others=>'0');
		bbb6 <= (others=>'0');
		bbb7 <= (others=>'0');
		bbb8 <= (others=>'0');
		
	elsif frame <= (5*b_len-1) and frame > (4*b_len-1) then --(199,249]
		temp:=(frame-4*b_len);
	   var := to_unsigned(temp,13);
		bbb1 <= b1(15 downto 0);
		bbb2 <= b2(15 downto 0);
		bbb3 <= b3(15 downto 0);
		bbb4 <= b4(15 downto 0);
		if unsigned(addr5(7 downto 0)) < var then
		    bbb5 <= b5(15 downto 0);
	   else
	      bbb5 <= (others=>'0');
	   end if;
		bbb6 <= (others=>'0');
		bbb7 <= (others=>'0');
		bbb8 <= (others=>'0');
		
	elsif frame <= (6*b_len-1) and frame > (5*b_len-1) then --(249,299]
		temp:=(frame-5*b_len);
	   var := to_unsigned(temp,13);
		bbb1 <= b1(15 downto 0);
		bbb2 <= b2(15 downto 0);
		bbb3 <= b3(15 downto 0);
		bbb4 <= b4(15 downto 0);
		bbb5 <= b5(15 downto 0);
		if unsigned(addr6(7 downto 0)) < var then
		    bbb6 <= b6(15 downto 0);
	   else
	      bbb6 <= (others=>'0');
	   end if;
		bbb7 <= (others=>'0');
		bbb8 <= (others=>'0');
		
	elsif frame <= (7*b_len-1) and frame > (6*b_len-1) then --(299,349]
		temp:=(frame-6*b_len);
	   var := to_unsigned(temp,13);
		bbb1 <= b1(15 downto 0);
		bbb2 <= b2(15 downto 0);
		bbb3 <= b3(15 downto 0);
		bbb4 <= b4(15 downto 0);
		bbb5 <= b5(15 downto 0);
		bbb6 <= b6(15 downto 0);
		if unsigned(addr7(7 downto 0)) < var then
		    bbb7 <= b7(15 downto 0);
	   else
	       bbb7 <= (others=>'0');
	   end if;
		bbb8 <= (others=>'0');
		
	elsif frame <= (8*b_len-1) and frame > (7*b_len-1) then --(349,399]
		temp:=(frame-7*b_len);
	   var := to_unsigned(temp,13);
		bbb1 <= b1(15 downto 0);
		bbb2 <= b2(15 downto 0);
		bbb3 <= b3(15 downto 0);
		bbb4 <= b4(15 downto 0);
		bbb5 <= b5(15 downto 0);
		bbb6 <= b6(15 downto 0);
		bbb7 <= b7(15 downto 0);
		if unsigned(addr8(7 downto 0)) < var then
		    bbb8 <= b8(15 downto 0);
	   else
	       bbb8 <= (others=>'0');
	   end if;
	  
	else
		bbb1 <= b1(15 downto 0);
		bbb2 <= b2(15 downto 0);
		bbb3 <= b3(15 downto 0);
		bbb4 <= b4(15 downto 0);
		bbb5 <= b5(15 downto 0);
		bbb6 <= b6(15 downto 0);
		bbb7 <= b7(15 downto 0);
		bbb8 <= b8(15 downto 0);
	end if;
	end if;
	end if;
end process;

process(clk,inflag,bbb1,bbb2,bbb3,bbb4,bbb5,bbb6,bbb7,bbb8)
  begin
    if inflag='1' then
    if clk'event and clk='1' then
t2 <=   signed(bbb1(15)&bbb1(15)&bbb1(15)&bbb1) +
		  signed(bbb2(15)&bbb2(15)&bbb2(15)&bbb2) +
		  signed(bbb3(15)&bbb3(15)&bbb3(15)&bbb3) +
		  signed(bbb4(15)&bbb4(15)&bbb4(15)&bbb4) +
		  signed(bbb5(15)&bbb5(15)&bbb5(15)&bbb5) +
		  signed(bbb6(15)&bbb6(15)&bbb6(15)&bbb6) +
		  signed(bbb7(15)&bbb7(15)&bbb7(15)&bbb7) +
		  signed(bbb8(15)&bbb8(15)&bbb8(15)&bbb8);
		  end if;
		  end if;
end process;
		  
temp2 <= std_ulogic_vector(t2);
softbits(15 downto 0) <= temp2(18 downto 3);



end bev;
